Transaction-Aware Network-on-Chip Resource Reservation
Packet-switched interconnect fabric, widely viewed as the de facto on-chip data communication standard in the many-core era, offers high throughput and excellent scalability. However, these benefits come at the price of router latency due to run-time multihop data buffering and resource arbitration, which account for the majority of on-chip transaction latency. In this work, the authors address the latency issue of on-chip network design and propose dynamic in-network resource reservation techniques that are guided by high-level data transaction information. This idea is motivated by the need to preserve existing abstraction and general-purpose network performance while optimizing for latency-critical events.