Utilizing Leveling Techniques in DDR3 SDRAM Memory Interfaces
The DDR3 SDRAM memory architectures support higher bandwidths with bus rates of 600 Mbps to 1.6 Gbps (300 to 800 MHz), 1.5V operation for lower power, and higher densities of 2 Gbits on a 90-nm process. While this architecture is undoubtedly faster, larger, and lower power per bit, just how does one go about interfacing a DDR3 SDRAM DIMM to an FPGA? Leveling is the key word. Without having the leveling feature built directly into the FPGA I/O structure, interfacing anything to a DDR3 SDRAM DIMM is going to be complicated, costly, and involve numerous external components. So, what is leveling and why is it so important?