Worst-Case Delay Analysis of Variable Bit-Rate Flows in Network-on-Chip With Aggregate Scheduling
Aggregate scheduling in routers merges several flows into one aggregate flow. The authors propose an approach for computing the end-to-end delay bound of individual flows in a FIFO multiplexer under aggregate scheduling. A synthetic case study exhibits that the end-to-end delay bound is up to 33.6% tighter than the case without considering the traffic peak behavior. Real-time applications such as multimedia and gaming boxes etc., require stringent performance guarantees, usually enforced by a tight upper bound on the maximum end-to-end delay. For the worst-case performance analysis, they derive the upper delay bound of a flow in a FIFO multiplexing and aggregate scheduling network.