Network ASIC provides incredible throughput performance at the cost of flexibility. Barefoot Networks' Tofino chip could help provide x86-like flexibility with ASIC performance.
It seems as if software has eaten the world, except for network hardware. Feature enablement is frustratingly slow in the network device space.
For example, it took major network vendors approximately four years to add VXLAN support to mainstream routers and switches. VXLAN makes perfect sense for the integration of virtualized networks and physical networks. Even with the agreement of major vendors such as Cisco and VMware, the rollout trailed the business drivers for years. The primary challenge is the ASIC-based approach used by the network industry. Barefoot Networks looks to eliminate the inflexibility of ASIC-based device design while maintaining performance via their new Tofino chip.
ASIC vs. x86 performance
Intel has done some amazing things with networking on x86, especially with Intel Xeon-based networking. The Data Plane Development Kit (DPDK) has achieved performance of 233 Gbps (347 Mpps) using a Xeon E5-2658. Telecom and application developers can build applications that provide any number of data services on packets transiting an Intel-based network function virtualized (NFV) instance.
x86-based network solutions have enjoyed the flexibility of software. VMware's NSX is a great example of a platform that quickly integrates new protocols and services via software. In many instances, 233 Gbps of performance is more than fast enough. However, the performance of x86 network is just a fraction of the throughput available via dedicated ASIC. ASIC chip maker Broadcom recently announced a processor capable of 1Tbps throughput in a much more network-friendly physical package that supports high-density network connectivity.
Network device manufacturers have long sacrificed flexibility for performance in system design. Unlike general computing processors, ASICs are purpose-built to accelerate specific algorithms. Protocols such as VXLAN require a redesign of the ASIC to perform high-throughput processing. Couple slow design, regression testing, and manufacturing into the equation and new protocol integration can take years to complete.
Lessons from GPU
Barefoot Networks recently presented at one of Gelstalt IT's Tech Field Day (TFD) events. During TFD, Barefoot Network discussed some of the lessons the company learned from the graphics processing units (GPU) industry. Companies such as NVIDIA have transformed themselves into high-performance compute (HPC) companies, as opposed to companies simply focused on the graphics industry. As a result of the lessons it learned, Barefoot Networks announced their Tofino platform.
Tofino is a programmable chip that enables line rate processing up to 6.5Tbps. Customers or network vendors can leverage the P4 programming language to customize white box solutions or fixed configuration products that offer x86-like flexibility while providing ASIC-like performance.
The company also provided a reference design to the Open Compute Project (OCP) that leverages the Wedge 100B switch. The Wedge 100 is a plan submitted to OCP by Facebook. Leveraging a Wedge 100B with a Tofino chip, customers the size of Facebook can build a custom switching platform with only the services needed for operation of their application. The limited feature switches improve performance and reliability by eliminating general purpose features not needed by the customer's applications. Vendors could use the same platform to provide 100G network products with just the services individual customers require.
It may take some time for enterprise customers to create custom code for white box switches. The more direct impact, however, is tighter release schedules for new services such as VXLAN. Tofino is a platform to watch carefully. As part of a long-term strategy, enterprise network managers need to pay attention to the chipsets in their network vendor products.
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