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IBM and Advanced Micro Devices have devised a new way of straining silicon–a design technique that improves chip performance–they claim will be cheaper, faster and easier to implement.
Called “Dual Stress Liners,” or DSL, the technique will ideally eliminate much of the complexity involved with strained silicon. Chips containing DSL are quietly already being sold, but both companies will start to use it in chips built on their 90-nanometer production processes in the first quarter, which will lead to greater proliferation.
According to early data, DSL improves transistor performance in its chips by 24 percent, but incorporating it does not decrease the number of good chips that come out of a wafer, meaning that it should be relatively inexpensive to adopt.
DSL also will heat up the processor-technology arms race between IBM and AMD and rival Intel. Intel uses a form of strained silicon with similar characteristics in its current 90-nanometer chips on sale now and will insert an enhanced version of strained silicon on its 65-nanometer chips coming toward the end of the year. (The nanometer measurements refer to the average feature size on the chips; a nanometer is a billionth of a meter.)
Its enhanced material will improve performance in its transistors by 30 percent, Intel says.
IBM, AMD and Intel will all provide details on their straining technologies at the International Electron Devices Meeting in San Francisco this week.
Strained silicon involves arranging the atoms in a layer of silicon in a manner that will allow electric carriers to move faster from one end of a transistor to another. In turn, faster transistors–the on/off switches inside chips–can lead to better chip performance and/or lower power consumption.
“The whole industry is looking for ways to make transistors switch faster,” said Nick Kepler, vice president of logic technology development at AMD.
To date, most companies have strained silicon by inserting a layer of germanium below the transistors. The larger germanium atoms pull the silicon atoms in the transistor layer apart from each other.
“It is sort of like driving through safety cones. If the cones are moved farther apart, you go faster,” Kepler said. Technically, from an electrical point of view, in tensile strain the effective mass of the electrons gets smaller, so it’s really like driving a smaller car, he explained, but the other image is mentally easier to grasp.
Tensile strain like this, however, only helps speed up the N-channel transistors, which carry electrons. It does not help the performance on P-channel transistors, where positive particles called holes travel. N-channel and P-channel transistors complement each other and are part and parcel of modern chips.
Straining through germanium is also tricky and expensive. Earlier, AMD tried to incorporate germanium strained silicon from AmberWave into its chips, but subsequently terminated the project. “There were manufacturing issues,” Kepler said.
In DSL, different straining materials are applied to the top of the transistor layer and then etched away from where they aren’t needed or from where they can even degrade performance. Materials that create tensile strain to benefit N-channel transistors are applied across the surface of the wafer; chemical etching then removes those materials away from the P-channel transistors.
Subsequently, a layer of material for compressing the silicon lattice, which benefits the P-channel transistors, is applied and etched. The materials for straining N-channel or P-channel transistors can be applied in either order.
“On the P-channel transistors, you want to increase the density of atoms because the holes can move more quickly,” said Nathan Brookwood, an analyst at Insight 64.
Kepler did not disclose the materials used but said they were fairly conventional nitride films and inexpensive. Plus, applying the straining materials after the transistor layer is complete is easier.
“It is the least disruptive way to do this,” Kepler said.
Intel currently uses a cap to obtain P-channel strain, similar to DSL, and a subterranean germanium layer for N-channel strain. The company would not elaborate on the new type of strain coming with 65-nanometer chips.
AMD quietly incorporated the technology in its most recent Athlon FX chips. These chips were made on the 130-nanometer process, an older chipmaking process. But in the first quarter, both AMD and IBM will adopt DSL for 90-nanometer chips.
Last August, AMD had begun to include a P-channel type of strained silicon in its chips. DSL replaces it.
Though Brookwood applauded the DSL technology, he also noted that it indicates the industry is possibly headed for a shortage of three letter abbreviations.
“We’ve run out of acronyms and started to reuse them,” he said.