Rambus, maker of RDRAM memory, will announce its Terabyte Bandwidth Initiative. This initiative will define a road map for technologies that will super charge bus transfers for multicored processors of the future.

An excerpt from Ars Technica:

For the past three years, Rambus has been laying the research groundwork for eventually answering a simple question: in a world with 100 cores on a single chip, how do you get enough data onto the chip to keep all those cores fed? At that point, a single system-on-chip (SoC) in a future game console may well need something on the order of a terabyte per second worth of bandwidth — some 20x the amount of bandwidth in today’s PlayStation 3.

The crux of the new initiative lies in three key technologies:

  • 32x data rate: 32 data transfers per clock cycles which would result in 1 TB/s bandwidth with 16 DRAMs at 500 MHz clock speed.
  • FlexLink for command/address routing: The command and address lines would use the same 32x signaling making for simpler implementation.
  • Fully Differential Memory Architecture: Use of differential signaling on the data, C/A and the clock lines.

Intel’s terascale computing initiative also focuses on several issues that will emerge in the future with massively multicored system-on-chip models.

More information:

Rambus aims for a terabyte of bandwidth (Inquirer)

Rambus proposes Terabyte per second memory initiative (TG Daily)

Rambus proposes Terabyte per second memory initiative (Tom’s Hardware)