RISC-V and Linux Foundations will partner to promote open source CPU

The Linux Foundation is firmly behind RISC-V, the extensible ISA which aims to unseat Arm in embedded, low-power, and IoT applications

The Linux Foundation and RISC-V Foundation announced yesterday a joint collaboration project to promote open source development and commercial adoption of the RISC-V instruction set architecture (ISA).

RISC-V is a new royalty-free ISA developed principally by researchers at UC Berkeley—with significant outside contributions—that is gaining popularity in Internet of Things (IoT), low-power, and embedded applications. Designs for higher-power use cases are also available. The Hi-Five Unleashed single-board computers feature a quad-core 1.5 GHz RISC-V CPU capable of directly running Linux.

SEE: Hardware spotlight: The Raspberry Pi (Tech Pro Research)

Though some devices that integrate RISC-V will use real-time operating systems rather than Linux, the use of Linux in development will be instrumental as existing tools are being extended to support the RISC-V ISA when developing software on traditional computers.

"This joint collaboration with the Linux Foundation will enable the RISC-V Foundation to offer more robust support and educational tools for the active RISC-V community, and enable operating systems, hardware implementations and development tools to scale faster," said Rick O'Connor, executive director of the RISC-V Foundation, in a press release.

In many ways, RISC-V is a hardware equivalent to the open source principles that guide the Linux project, as the ISA is open source, is not subject to patent encumbrances, and is available under the BSD license. With this license, organizations that wish to implement or extend RISC-V in commercial products are not compelled to disclose their changes to the community at large. This makes it particularly appealing for commercial use in embedded devices, as licensing fees for Arm or MIPS ISAs—both of which are fundamentally RISC in principle—can be avoided by using RISC-V. Likewise, RISC-V CPUs are not restricted to a single manufacturer.

Why does this matter?

Before 2000, there was a much wider variety of instruction set architectures commonly in use in desktop, server, mobile, and embedded applications. These are mostly transparent to end users, though when Apple transitioned away from PowerPC CPUs in 2006 in favor of Intel x86-64 CPUs, the hegemony of x86-64 began in the desktop market.

For mobile and embedded computing, Arm has long been the dominant player—for which an oversupply of cheap Arm processors have led to the rise of mass-produced single-board computers (SBCs) like the Raspberry Pi and competitors. The lack of diversity in these markets causes problems which are more acutely felt when hardware vulnerabilities such as Spectre and Meltdown are discovered.

As alternatives like Alpha, SuperH, MIPS, and even Intel's own Itanium processors have fallen by the wayside, organizations using those ISAs in their products have had difficult adjustment periods transitioning away, while patent encumbrances largely prevent third parties from continuing development or providing drop-in replacements for those technologies. RISC-V's open nature prevents these issues, as it is possible for any organization to extend or customize their own implementation, and any organization can produce their own RISC-V processors.

RISC-V is already receiving wide industry adoption, with NVIDIA planning to use RISC-V as the basis for the next-generation version of their Falcon microcontroller. Similarly, Western Digital plans to adopt RISC-V for drive controllers, and projects involving on-disk computing capabilities. The company has pledged to transition "its own consumption of processors - over one billion cores per year - to RISC-V."

The big takeaways for tech leaders:

  • The Linux Foundation and RISC-V Foundation announced a joint collaboration project to promote open source development and commercial adoption of the RISC-V instruction set architecture (ISA).
  • The open source license of RISC-V allows for long-term hardware deployment without risk of vendors abandoning the product, creating difficult transition periods away from those products.

Also see

Image: SiFive

About James Sanders

James Sanders is a technology writer for TechRepublic. He covers future technology, including quantum computing, AI, and 5G, as well as cloud, security, open source, mobility, and the impact of globalization on the industry, with a focus on Asia.

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