Western Digital is open sourcing their implementation of RISC-V and development tools to promote adoption of the ISA across storage and other industries.
On Tuesday, Western Digital, an early adopter and vocal proponent of RISC-V, announced plans to open source their implementation of the RISC-V ISA and associated development resources, providing the ability for the open source community to utilize their implementation of the architecture in their own products as well as iterate on it to meet the needs of their own products.
SweRV Core EHX1, the first generation of RISC-V processors at Western Digital, is a 32-bit, 2-way superscalar, 9 stage pipeline core capable of clock speeds up to 1.8 GHz, produced on a 28mm CMOS process, at 4.90 CoreMark/MHz, which slightly outperforms ARM Cortex A15 (at 4.72 CoreMark/MHz). For their own products, Western Digital touts it as being fit for "embedded devices supporting data-intensive edge applications, such as storage controllers, industrial IoT, real-time analytics in surveillance systems, and other smart systems." Plans for SweRV Core will be released in Q1 2019.
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Likewise, the SweRV Instruction Set Simulator (ISS) is a utility which offers full test bench support for RISC-V processors, which Western Digital "developed independently from the SweRV Core to ensure RISC-V cores are executing instructions properly." SweRV ISS is available now on GitHub, licensed under the GNU GPL, version 3.
The storage giant is also releasing OmniXtend, a "fully open networking protocol for exchanging coherence messages directly with processor caches," which is intended for connecting persistent memory to processors. This is useful in creating machine learning accelerators, as well as memory-centric devices which leverage RISC-V CPUs, including multi-socket RISC-V solutions, and heterogeneous solutions which share data between GPUs or other CPU types with RISC-V.
Internally, Western Digital is planning to convert their entire product lineup to leverage RISC-V, which the company indicates in a press release that it "expects to be shipping two billion RISC-V cores annually," once the transition is complete, adding that "the company is committed to advancing RISC-V technology for use in mission-critical applications so that it can be deployed in its products."
This transition will save the company a substantial amount in licensing fees it presently pays to Arm for use of the Arm ISA in products, including disk drive controllers.
The big takeaways for tech leaders:
- Western Digital is planning to release plans for SweRV Core, their first RISC-V CPU, to bolster industry adoption of the open source ISA.
- The use of RISC-V will save Western Digital costs it currently pays to license the Arm ISA in current products.
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