Intel and IBM, in separate releases, announced a new more energy efficient way of making the tiny gates which make up semiconductors.
First to be seen in dual and quad core server and PC microprocessors late this year, the new Intel chips will be available before IBM’s production.
Specifically, the new gate design consists of replacing the gate dielectric material from silicon dioxide to a hafnium-based material which will reportedly make each tiny gate more efficient.
Because of the new dielectric material the gate itself will have to be made of a new material also, replacing polysilicon with an as yet unspecified material.
The next generation of microprocessors will use 45-nanometer technology which, by itself would improve performance, but because the traditional gate dielectric material would be so thin that it would perform poorly, the new hafnium-based technology appears to be necessary to advance to the next level of chip size.
Meanwhile, Hewlett-Packard recently announced a new nanoscale crossbar chip architecture which would allow up to 8 times more traditional gates to be placed on a chip without reducing the size of the individual gates. See the January 24 issue of “Nanotechnology” for details on this research (http://www.iop.org/EJ/toc/0957-4484/18/3).
Nano/CMOS architectures using a field-programmable nanowire interconnect http://www.iop.org/EJ/article/0957-4484/18/3/035204/nano7_3_035204.pdf