The authors propose a parallel implementation of the Cell Average Constant False Alarm Rate (CA-CFAR) algorithm in reconfigurable hardware. The design is based on a parallel processing scheme employing extensive data reuse and synchronized sliding windows over the input data sequence. A scalable parallel structure is designed and mapped on Xilinx Virtex II Pro technology. ...

Within packet processing systems, lengthy memory accesses greatly reduce performance. To overcome this limitation, network processors utilize many different techniques, for example, utilizing multilevel memory hierarchies, special hardware architectures, and hardware threading. In this paper, the authors introduce multi-level memory architecture for counting Bloom filters. Based on the probabilities of incrementing of the counters in ...