In this paper, the authors present FPGA-based design of hybrid adder with the optimal bit-width configuration(out of a large number of possible configurations) of each of the sub-adders constitute the proposed hybrid adder using a high level automated methodology. Algebraic optimization model for the hybrid adder is built to produce the best choice of types ...

The hardware description and implementation of adaptive Infinite-Impulse-Response (IIR) filters for real-time applications is an important and challenging designing issue. This paper is hardware description of digital adaptive IIR filters for implementing on Field Programmable Gate Array (FPGA) chips. The direct architecture is considered for IIR filter designing and Equation-Error (EE) Least Mean Square (LMS) ...

In this paper, the authors focus on the enhancement of the practical performance of an algorithm and data structures. It provides a way to achieve the effect on performance parameters of operating system. The proposed paper has been done about the performance of a number crunching program (matrix multiplication) by varying the swap area at ...

In general, high energy cosmic ray experiment deal with a large number of detector signals. A few prime signal parameters are need to be measured, recorded on a coherent detection of signals, called trigger. Triggers are random in time. It is also necessary to monitor continuously the performance of the detectors. The authors’ paper is ...

In this paper, the authors present a design of efficient digital Vedic multiplier using the Vedic sutras from ancient Indian Vedic mathematics. If they are looking towards the signal processing, they will find multipliers and adders plays a very important roll. In fact if they make their focus they can see speed of the digital ...

A priority interrupt controller is a hardware designed chip which acts as an overall system manager to efficiently handle the multiple interrupts that tend to occur from the varied number of peripheral devices. Hence, it relieves the system’s CPU from the task of polling in a multi-level priority system. This paper deals with implementation of ...

CPU scheduling should preserve fairness and avoid processes from do not ever obtain CPU. Modern operating system era faces multitasking on computer operational environment. If CPU scheduling is efficient, high computation could be done correctly and system could be retained stable. One criterion that must be achieved by scheduling algorithm is minimization average waiting time ...

To preserve the electronic fitness records of data mining applications, data perturbation is used. It is a form of privacy-preserving data mining. An improved amount and range of information stored in databases has direct to an enhancement in the desire for ranked and “Best match” queries. Such queries are mainly applicable when dealing with privacy-sensitive ...

The proposed GF(2193) is based on an efficient Montgomery add and double algorithm, also the karatsuba-offman multiplier and Itoh-Tsjuii algorithm are used as the inverse component. The hardware design is based on optimized Finite State Machine (FSM), with a single cycle 193 bits multiplier, field adder and field squarer. The different optimization at the hardware ...

The essential problem in many data mining applications is mining frequent item sets such as the discovery of association rules, patterns and many other important discovery tasks. Fast and less memory utilization for solving the problems of frequent item sets are highly required in transactional databases. Methods for mining frequent item sets have been implemented ...