International Journal of Computer Theory and Engineering (IJCTE)
In this paper, the authors present the design of low power i.e. 0.69mW and 700MHz, 8 x 8-bit digital multiplier providing a better performance and lower power dissipation than the conventional linear array multipliers in two folds of speed and power consumption. The modified pair-wise and parallel addition algorithms provide high speed multiplication and lower power dissipation in this paper. The power performance of individual block is pre evaluated to identify the most power consuming element and attempt is to select the most efficient topology to reduce the power consumption of entire multiplier while maintaining the high operating frequency.