Engineering and Technology Publishing
In this paper, the authors present its own design of 12-bit pipeline ADC which has an operating frequency of 8 MHz and consists of 4 stages only. This design is a pipelined ADC with four 3-bit stages (each stage resolves two bits). By doing so; the chip area can be decreased along with minimized power dissipation. In the paper's design, VIN, is first sampled and held steady by a Sample-and-Hold (S&H), while the flash ADC in stage one quantizes it to three bits. The 3-bit output is then fed to a 3-bit DAC (accurate to about 12 bits), and the analog output is subtracted from the input.