16-Bit Arithmetic and Logic Unit Design Using Mixed Type of Modeling in VHDL

In this paper, the authors explain the design and implementation of 16-bit ALU (Arithmetic and Logic Unit) using VHDL by using mixed style of modeling in Xilinx ISE 8.1i. The ALU takes two16-bits numbers and performs different principal arithmetic and logic operations like addition, multiplication, logical AND, OR, XOR, XNOR. The major focus of concern in this ALU is the multiplication operation using radix-4 booth algorithm and bit-pair recording technique which increases the speed of multiplication operation.

Provided by: International Journal of Engineering Research and Applications (IJERA) Topic: Hardware Date Added: Mar 2014 Format: PDF

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