16nm planar process CMOS SRAM cell design: Analysis of Operating Voltage and Temperature Effect

Provided by: Creative Commons
Topic: Storage
Format: PDF
CMOS devices are scaling down to nano ranges resulting in increased process variations and short channel effects which not only affect the reliability of the device but also performance expectations. The SRAM design uses the smallest transistors possible and is also susceptible to reliability issues and process variations, making it an ideal benchmark circuit to compare the two technologies. Low power Static-Random Access Memories (SRAM) has become a critical component in modern VLSI systems. They occupy a large portion of area and accounts for a major component of power consumption in today's VLSI circuits.

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