2-Bit CMOS Comparator by Hybridizing PTL and Pseudo Logic
In this paper, an area and power efficient hybrid comparator is proposed by hybridizing PTL and Pseudo logic design. This hybrid comparator is proposed to improve area and power in 120 nm technology and compared with this paper. To improve area and power minimum number of transistor logic is used in the proposed hybrid comparator. The proposed comparator has been designed and simulated using DSCH 3.1 and Microwind 3.1 on 120 nm. Also the simulation of layout and parametric analysis has been done for the proposed comparator design.