3.5-D Blocking Optimization for Stencil Computations on Modern CPUs and GPUs

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
Stencil computation sweeps over a spatial grid over multiple time steps to perform nearest-neighbor computations. The bandwidth-to-compute requirement for a large class of stencil kernels is very high, and their performance is bound by the available memory bandwidth. Since memory bandwidth grows slower than compute, the performance of stencil kernels will not scale with increasing compute density. The authors present a novel 3.5D-blocking algorithm that performs 2.5D-spatial and temporal blocking of the input grid into on-chip memory for both CPUs and GPUs.

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