University of Malta
Two diverse manufacturing techniques for building 3-D integrated systems are vertical integration with Through-Silicon-Vias (TSVs), also referred as 3-D TSV integration, and 3- D monolithic integration. In this paper, the authors present a hybrid integration scheme that combines these two approaches, taking into account their existing technology limits, into a disruptive paradigm called 3.5-D integration. Their novel integration supports circuit-partitioning both at the gate and block level with unprecedented benefits in cost. To demonstrate the effectiveness of 3.5-D integration, they chose as case study a 288-core MPSoC and they made hypothesis on the manufacturing and test cost.