3-Tier Reconfiguration Model For FPGAs Using Hardwired Network on Chip

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Provided by: Delft University of Technology
Topic: Hardware
Format: PDF
The authors envision that future Field-Programmable Gate Arrays (FPGAs) will use a Hardwired Network on Chip (HWNoC) as a unified interconnect for functional communications (data and control) as well as configuration (bitstream for soft IPs). In this paper, they present a 3-tier reconfiguration model that uses the HWNoC as the underlying platform to realize dynamic loading, starting, and stopping of applications. The model ensures that applications are guaranteed their required resources (LUTs, communication, memory). Resource allocation is performed globally at design time.
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