32nm Based High-Speed Low-Power Calibrated Flash ADC Comparator with Improved ENOB

In this paper, the authors have proposed a low power high speed CMOS comparator using Dual Mode Logic (DML) for flash type analog to digital converter, the simulation model of DML based CMOS logic simplification is to identify a system that improves the hardware utilization rate from 57.14% to 100% by improving the delay and power consumptions occurred in data converter circuits. The proposed paper whose layout simulation with extended DML logic is implemented and its performance characteristics are studied using Microwind simulator.

Provided by: International Journal Of Engineering And Computer Science Topic: Hardware Date Added: Jun 2015 Format: PDF

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