Provided by: Delft University of Technology
Date Added: Oct 2013
Selecting appropriate and efficient test flow for a 3D Stacked IC (3D-SIC) is crucial for overall cost optimization. This paper presents 3D-COSTAR, a tool that considers costs involved in the whole 3D-SIC chain, including design, manufacturing, test, packaging and logistics (e.g. related to shipping wafers between a foundry and a test house); and provides the estimated overall cost and cost breakdown for a given input parameter set (e.g., test flows, die yield and stack yield).