3D-NoC: Reconfigurable 3D Photonic On-Chip Interconnect for Multicores

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Provided by: University of Applied Sciences Rapperswil
Topic: Hardware
Format: PDF
The power dissipation of metallic interconnects in future multicore architectures are projected to be a major bottleneck as the authors scale to sub-nanometer regime. This has motivated researchers to develop alternate power-efficient technology solutions to the performance limitations of future multicores. Nanophotonic Interconnects (NIs) is a disruptive technology solution that is capable of delivering the communication bandwidth at low power dissipation when the number of cores is scaled to large numbers. Similarly, 3D stacking is another interconnects technology solution that can lead to low energy/bit for communication.
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