Delft University of Technology
In this paper, the authors address the design of wide-operand addition units in the context of the emerging Through-Silicon Vias (TSV) based 3D Stacked IC (3D-SIC) technology. To this end they first identify and classify the potential of the direct folding approach on existing fast prefix adders, and then discuss the cost and performance of each strategy. Their analysis identifies as a major direct folding drawback the utilization of different structures on each tier. Thus, in order to alleviate this, they propose a novel 3D stacked hybrid prefix/carry-select adder with identical tier structure, which potentially makes the manufacturing of hardware wide-operand adders a reality.