4-Bit Brent Kung Parallel Prefix Adder Simulation Study Using Silvaco EDA Tools
In IC design environment, the chip performance is influence by design environment, schematic and sizing parameter of the transistor. Therefore, this paper is an attempt to investigate the performance of 4-bit Brent-Kung parallel prefix adder using Silvaco EDA tools and targeted to 0.18um Silterra technology. This paper is to review the performance of the adder by forming different of transistors gate sizing and schematics. Furthermore, the paper been carried out by implementing Brent-Kung adder in basic logic gate and compound gate, then simulate the design in various sizes of transistors in order to see the effects on propagation delay, power consumption and the number of transistors used.