4-Bit Ripple Carry Adder of Two-Phase Clocked Adiabatic Static CMOS Logic: A Comparison with Static CMOS

Recently, clock and logic speeds have been increased for enhancing the performance of mobile and wireless devices; hence, it is important to design Integrated Circuits (ICs) that help achieve high energy efficiency This paper demonstrates the low-energy operation of a Two-Phase clocked Adiabatic Static CMOS Logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit Ripple-Carry Adder (RCA) employing 2PASCL circuit technology. Energy dissipation in the 2PASCL RCA is 71.3% lesser than that in a static CMOS RCA at transition frequencies of 10-100MHz.

Provided by: Gifu University Topic: Hardware Date Added: Jul 2009 Format: PDF

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