Provided by: Gifu University
Date Added: Jul 2010
In this paper, the authors present the simulation results of a 4x4-bit array Two-Phase clocked Adiabatic Static CMOS Logic (2PASCL) multiplier using 0.18 um standard CMOS technology. They also propose a new design of 2PASCL XOR which reduces the number of transistors as well as the power consumption. Analytical method to compare the lower current flow in adiabatic circuit is also presented. At transition frequencies of 1 to 100 MHz, 4x4-bit array 2PASCL multiplier shows a maximum of 55% reduction in power dissipation to that of a static CMOS.