63X37 EGLDPC Error Detection Using Majority Logic Decoder
Error identification is process of test detection. While transferring the data many errors will occur including memory utilization due to this the memory utilization is increase. To detect the errors and checking them with effective memory utilization using low density parity checker is possible. For this process, a serial logic circuit is implemented and is known as majority logic on the decoder side. The entire process explains a 63X37 Euclidean geometry method. The complete paper is executed in xilinx14.2 version on vertex 6 kit.