For higher order multiplications, a huge number of adders or compressors are to be used to perform the partial product addition. The authors have reduced the number of adders by introducing special kind of adders that are capable to add five/six/seven bits per decade. These adders are called compressors. Binary counter property has been merged with the compressor property to develop high order compressors. Uses of these compressors permit the reduction of the vertical critical paths. A 16x16 bit multiplier has been developed using these compressors.