A 1991 Mpixels/s Intra Prediction Architecture for Super Hi-Vision H.264/AVC Encoder

Provided by: EURASIP
Topic: Security
Format: PDF
This paper presents an H.264/AVC intra prediction design for Super Hi-Vision (SHV) video. Due to huge throughput requirements, design challenges such as data dependency and complexity become even more critical. To solve these problems, the authors first propose an interlaced block reordering scheme together with a Coarse-to-Fine Mode Decision (CFMD) strategy to resolve the data dependency between intra mode decision and reconstruction. Circuit's area is reduced in the meantime with CFMD. They also propose a probability-based reconstruction scheme to solve the problem from long pipeline latency. As a result, hardware complexity in terms of the product of area and frequency is reduced by 74%. The maximum throughput reaches 1991 Mpixels/s for 7680 x 4320p 60 fps video. Total logic gate count is 451.5k in 65 nm library.

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