Provided by: Institute of Electrical & Electronic Engineers
In this paper, the authors propose decoder architecture for Low Density Parity-Check Convolutional Code (LDPCCC). Specifically, the LDPCCC is derived from a Quasi-Cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure, the proposed LDPCCC decoder adopts dynamic message storage in the memory and uses a simple address controller. The decoder efficiently combines the memories in the pipelining processors into a large memory block so as to take advantage of the data-width of the embedded memory in a modern Field-Programmable Gate Array (FPGA). A rate-5/6 QC-LDPCCC has been implemented on an Altera Stratix FPGA. It achieves up to 2.0 Gb/s throughput with a clock frequency of 100 MHz.