International Journal of Computational Engineering Research (IJCER)
After analyzing the advantages and disadvantages of all the general algorithms adopted in designing square root on FPGA chips with pipeline technology, a proposed algorithm based on digit by digit calculation method is discussed. The algorithm is realized on the ModelSim SE 6.3f development platform with VHDL language and the simulation results show that it is characterized by occupying less resource as well as processing is in a faster speed. Therefore it is an effective algorithm for implementing square root on commonly-used FPGA chips with pipeline technology. Square root operation deserves attention because of its frequent use in a number of applications.