A 5.35mm2 10GBASE-T Ethernet LDPC Decoder Chip in 90 nm CMOS
A partially parallel Low Density Parity Check (LDPC) decoder compliant with the IEEE 802.3an standard for 10GBASE-T Ethernet is presented. The design is optimized for minimum silicon area and is based on the layered offset-min-sum algorithm which speeds up the convergence of the message passing decoding algorithm. To avoid routing congestion the decoder architecture employs a novel communication scheme that reduces the critical number of global wires by 50%. The prototype LDPC decoder ASIC (Application-Specific Integrated Circuit), fabricated in 90nm CMOS (Complementary Metal-Oxide-Semiconductor), occupies only 5.35mm2 and achieves a decoding throughput of 11.69 Gb/s at 1.2V with an energy efficiency of 133 pJ/bit.