International Journal of Emerging Technology and Advanced Engineering (IJETAE)
A low power and high gain TransImpedance Amplifier (TIA) in 0.18µm CMOS technology is presented. TIA with better performance is realized by reducing the effects of input parasitic capacitor. A negative admittance output stage enables the transimpedance gain and the bandwidth to be improved. Cadence tools were conducted for this proposed TIA by utilizing RF transistor model based on 0.18µm HV CMOS process. Simulations are done with a single supply and the presence of a 50fF photodiode capacitance and 5fF loading capacitance.