A 80Ms/sec 10bit Pipelined ADC Using 1.5Bit Stages and Built-In Digital Error Correction Logic
Use of pipelined ADCs is becoming increasingly popular both as stand-alone parts and as embedded functional units in SoC (System-on-Chip) design. They have acceptable resolution and high speed of operation and can be placed in relatively small area. The design is implemented in 0.18uM CMOS process. The design includes a folded cascode op-amp with a unity gain frequency of 200MHz at 88deg. Phase margin and a DC gain of 75dB. The circuit employs a built in sample and hold circuit and a three phase non-overlapping clock.