A Better Performance Multiplier with the Spurious Power Suppression Technique

In this paper, the authors provide the experience of applying an advanced version of their former Spurious Power Suppression Technique (SPST) on multipliers for high-speed and low-power purposes. To filter out the useless switching power, there are two approaches, i.e., using registers and using AND gates, to assert the data signals of multipliers after the data transition. The SPST has been applied on both the modified booth decoder and the compression tree of multipliers to enlarge the power reduction.

Provided by: Creative Commons Topic: Hardware Date Added: Jun 2014 Format: PDF

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