A Built-In Redundancy-Analysis Scheme for RAMs with 2D Redundancy Using 1D Local Bitmap

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Provided by: edaa
Topic: Hardware
Format: PDF
Built-In Self-Repair (BISR) technique is gaining popular for repairing embedded memory cores in System-On-Chips (SOCs). To increase the utilization of memory redundancy, the BISR technique usually needs to perform Built-In Redundancy-Analysis (BIRA) algorithm for redundancy allocation. This paper presents an efficient BIRA scheme for embedded memory repair. The BIRA scheme executes the 2D redundancy allocation based on the 1D local bitmap. This enables that the BIRA circuitry can be implemented with low area cost. Also, the BIRA algorithm can provide good repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories).
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