Provided by: Academy & Industry Research Collaboration Center
Date Added: Jun 2011
In this paper, the authors propose a new bus coding scheme for reducing the crosstalk in System-on-Chip (SoC). As circuit geometries become smaller, wire interconnections become closer together and taller, thus increasing the cross-coupling capacitance between nets. At the same time, parasitic capacitance to the substrate becomes less as interconnections become narrower and cell delays are reduced as transistors become smaller. With circuit geometries at 0.25 micron and above, substrate capacitance is usually the dominant effect.