The University of Tulsa
The authors present a network processor architecture which is based on asynchronous microcoded controller hardware. The focus of this work is not on the processor architecture, but rather on the asynchronous microcoded style used to build such architecture. This circuit style tries to fill the performance gap between a specialized ASIC and a more general network processor implementation. It does this by providing a microcoded framework which is close in performance to ASICs and is also programmable at the finer granularity of microcode.