A Case for Bufferless Routing in On-Chip Networks

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Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
Buffers in on-chip networks consume significant energy, occupy chip area, and increase design complexity. In this paper, the authors make a case for a new approach to designing on-chip interconnection networks that eliminates the need for buffers for routing or flow control. They describe new algorithms for routing without using buffers in router input/output ports. They analyze the advantages and disadvantages of bufferless routing and discuss how router latency can be reduced by taking advantage of the fact that input/output buffers do not exist. Their evaluations show that routing without buffers significantly reduces the energy consumption of the on-chip cache/processor-to-cache network, while providing similar performance to that of existing buffered routing algorithms at low network utilization (i.e., on most real applications).
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