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In this paper, the authors introduce a chip ID generation circuit, which uses process variations that appear during the physical execution of an FPGA. The researcher introduced for the first time the ROs digital circuit with the aim of emphasizing the uncontrollable effect of silicon process variations at the delay of the digital component interconnection. After that, different constructions based on process variations start to appear. The digital circuit analyzed is a modification of the latch based circuit with the scope to minimizing the hardware resource usage and to fit an FPGA implementation.