A Co-Synthesis Methodology for Power Delivery and Data Interconnection Networks in 3D ICs

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
A stable voltage supply is critical for Multi-Processor System-on-Chips (MPSoCs) to operate at near-optimal performance levels. The problem of IR drops in a Power Delivery Network (PDN) is very severe in 3D MPSoCs with Network-on-Chip (NoC) fabrics where the current in the PDN increases proportionally with the number of device layers. At the same time, with the increasing core counts in today's power-hungry MPSoCs, the already hard problem of voltage island-aware Network-on-Chip (NoC) design has become even more challenging. Even though the PDN and NoC design goals are non-overlapping, both the optimizations are interdependent.

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