Institute of Electrical & Electronic Engineers
STT-RAM is an emerging NVRAM technology that promises high density, low energy and a comparable access speed to conventional SRAM. This paper proposes a hybrid L1 cache architecture that incorporates both SRAM and STT-RAM. The key novelty of the proposal is the exploition of the MESI cache coherence protocol to perform dynamic block reallocation between different cache partitions. Compared to the pure SRAM-based design, the authors' hybrid scheme achieves 38% of energy saving with a mere 0.8% IPC degradation while extending the lifespan of STTRAM partition at the same time.