Now-a-days, low power and high stability have been the main theme is designing SRAM, due to this the authors are moving towards the new technologies. As a result, they are facing new challenges in developing the new technologies. These technologies lead to the implementation of different types of SRAM’s. From the last few decades, the scaling down of CMOS devices have been taking place to achieve better performance in terms of speed, power dissipation, size and reliability. Basically, the performance of the SRAM cell is measured based on static noise margin and write trip point.