A Comparative Study of Dynamic Latch Comparator

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Provided by: Seek Digital Library
Topic: Hardware
Format: PDF
In this paper, the authors present the comparison between CMOS dynamic latch comparators. The circuit has been simulated using SPICE tool with 0.35µm technology, supply voltage of 3 V and 3.3 V respectively. The circuits studied and simulated in this paper are pre-amplifier dynamic latch circuit that consists of a preamplifier followed by a double regenerative dynamic latch and the buffered dynamic latch circuit that consists of a basic dynamic latch comparator followed by an inverter buffer stage.
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