A Comparative Study of Interconnect Circuit Techniques for Energy Efficient On-Chip Interconnects

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Provided by: International Journal of Computer Applications
Topic: Hardware
Format: PDF
The aggressive technology scaling in VLSI leads to decrease the size of chip. Such continual miniaturization of VLSI devices has strong impact on interconnects in several ways. Interconnects in high speed applications suffer from crosstalk, signal delay and ground noise, causing degradation of system performance. Thus, interconnects are becoming a limiting factor in determining circuit performance. This paper presents a comparative study on different interconnect circuit techniques for on-chip interconnects. The authors have compared different circuit structure by placing on RC and RLC interconnects.
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