A Compiler Framework for Optimization of Affine Loop Nests for GPGPUs

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Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
GPUs are a class of specialized parallel architectures with tremendous computational power. The new Compute Unified Device Architecture (CUDA) programming model from NVIDIA facilitates programming of general purpose applications on their GPUs. However, manual development of high-performance parallel code for GPUs is still very challenging. In this paper, a number of issues are addressed towards the goal of developing a compiler framework for automatic parallelization and performance optimization of affine loop nests on GPGPUs: approach to program transformation for efficient data access from GPU global memory, using a polyhedral compiler model of data dependence abstraction and program transformation; determination of optimal padding factors for conflict-minimal data access from GPU shared memory and model-driven empirical search to determine optimal parameters for unrolling and tiling.
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