A Complete Real-Time 802.11a Baseband Receiver Implemented on an Array of Programmable Processors

In this paper, the authors report the design and software implementation of a real-time digital baseband receiver compliant with the IEEE 802.11a standard on the AsAP2 platform, a DSP chip multiprocessor. The computational platform consists of an array of programmable processors and configurable accelerators interconnected in a 2-D mesh network that are well matched for implementing complex DSP and embedded systems such as wireless and video applications. The receiver has full functionality including frame detection, timing synchronization; carrier frequency offset compensation, and channel equalization.

Provided by: Institute of Electrical & Electronic Engineers Topic: Hardware Date Added: May 2009 Format: PDF

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