A Complexity-Effective Out-of-Order Retirement Microarchitecture

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Provided by: Universidad Politecnica de Madrid
Topic: Hardware
Format: PDF
Current superscalar processors commit instructions in program order by using a Re-Order Buffer (ROB). The ROB provides support for speculation, precise exceptions, and register reclamation. However, committing instructions in program order may lead to significant performance degradation if a long latency operation blocks the ROB head. Several proposals have been published to deal with this problem. Most of them retire instructions speculatively. However, as speculation may fail, checkpoints are required in order to rollback the processor to a precise state, which requires both extra hardware to manage checkpoints and the enlargement of other major processor structures, which in turn might impact the processor cycle.
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