A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
Future processor chip implementations are expected to be composed of 3D die stacks that could include multiple dies fabricated in diverse fabrication technologies. One design possibility which is particularly attractive is the idea of stacking cache or memory on top of a die that contains multiple CPU cores. Future many-core processors are expected to have large memory bandwidth requirements and stacking cache or memory directly on top of the cores is one possible way of providing the required bandwidth.

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