A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors

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Provided by: European Design and Automation Association
Topic: Hardware
Format: PDF
Non-volatile processor has become an emerging topic in recent years due to its zero standby power, resilience to power failures and instant on feature. This paper first demonstrated a fabricated nonvolatile 8051-compatible processor design, which indicates the ferroelectric nonvolatile version leads to over 90% area overhead compared with the volatile design. Therefore, the authors proposed a compare and compress recovery architecture, consisting of a Parallel Run-Length Codec (PRLC) and a state table logic, to reduce the area of nonvolatile registers.
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